In conventional fabrication of semiconductor devices, semiconductor wafers are processed in batch, and a large number of complicated devices are formed on a single wafer. With rapid development of very large scale integration (VLSI), wafers are developed toward higher integration density and miniaturization. In the fabrication process, the critical dimensions of integrated circuits are reduced, which raises a higher requirement for lithography processes. However, due to the restriction by the light source wavelength of conventional immersion scanners, conventional lithography cannot meet requirements of processes below 28 nanometers (nm). In order to satisfy the requirements of processes below 28 nm, extreme ultraviolet (EUV) lithography techniques are used. EUV lithography is an emerging technology utilizing extreme ultraviolet light to transfer a circuit layout pattern from a reflective EUV photomask to photoresist overlying a semiconductor substrate.
EUV lithography can be used to form self-aligned vias through interlayer dielectric for the creation of an electrical interconnect structure. Conventionally, photoresist films for exposure by EUV light are formed on an antireflective coating such as a silicon-containing antireflective coating (Si-ARC) that is in turn formed on a planar surface of a material such as a planarization layer. The planarization layer conventionally lies over an etch stop layer formed on the interlayer dielectric. After exposure of the photoresist film and selective etching of the planarization layer to form trenches, the antireflective coating is removed. Further, it may be required that residue from the antireflective coating be removed before further processing of the semiconductor substrate to avoid generating defects on the wafer. Otherwise, the defects generated from the antireflective coating residue may cause yield loss for the fabricated integrated circuit. Also, if it is determined that the etch of the planarization layer is misaligned with underlying objects to be contacted, a rework process may require a wet clean removal of the antireflective coating and a separate strip process to remove the planarization layer before the EUV patterning process is repeated. The Si-Arc removal in a rework process may generate defects on the wafer which would cause yield loss.
Accordingly, it is desirable to provide embodiments of methods for fabricating integrated circuits including improved patterning schemes for use with EUV lithography. It is further desirable to provide embodiments of a method suitable for fabricating an integrated circuit in which the risk of defect generation is minimized and the fabrication is cost effective. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.